This invention relates to semiconductor devices, and more particularly to self refresh circuitry of the type used in semiconductor dynamic memory devices.
Dynamic read/write memory devices are constructed as illustrated, for example, in U.S. Pat. No. 4,071,801, issued to White, McAdams and Redwine (a 16K DRAM) or U.S. Pat. No. 4,293,993, issued to McAlexander, White and Rao (a 64K DRAM), both assigned to Texas Instruments. These dynamic RAMs must be periodically refreshed because data is stored in capacitors and is subject to leakage. Self refresh arrangements for DRAMs are shown in U.S. Pat. No. 4,207,614, issued to Lionel S. White and G. R. Mohan Rao, U.S. Pat. No. 4,336,647 issued to David J. McElroy, both assigned to Texas Instruments, and in pending application Ser. No. 401,688 filed July 26, 1982, now U.S. Pat. No. 4,494,222.
In prior self-refresh methods for DRAMs, degradation of the access speed for normal read and write cycles may be caused by the addition of the circuitry needed to implement the refresh functions. Or, the refresh counter may have employed additional clocks or other circuitry not compatable with the normal functions. Self-refresh is an option which is often left unused, especially in large memory systems, so the refresh counter should be of relatively simple construction and not add to complexity of the manufacturing process or bar layout.
It is the principle object of this invention to provide improved high-speed self-refresh circuits for semiconductor integrated circuits such as dynamic memory devices. Another object is to provide improved compatability between operation of refresh counter circuitry and normal read/write access in a dynamic RAM, as well as simplified construction.